Senior Tech Lead 30 views

Cyient brings more than 20 years of experience in semiconductor and software systems solutions and services. We offer a complete capability across the semiconductor value chain, from design services to custom turnkey ASIC solutions. Our strong technical and domain expertise with a robust partnership ecosystem makes us a trusted global semiconductor partner, giving our engineers the opportunity to work on cutting edge projects, to make a difference and to develop themselves.

Why work for Cyient:

Our Semiconductor team works on cutting edge technology from AI led chip design to IOT and embedded intelligence. This is your chance to work for an innovative team and build your technical prowess. Our engineers have the opportunity to work across the product lifecycle. Are you looking to expand your skills across the value chain Our project leads recognize talent and growth aspirations, helping you expand your technical skills. Our semiconductor business serves multiple industries such as industrial, medical, and automotive. We are uniquely positioned to bring innovation from each domain for our custom ASIC solutions and semiconductor services. Cyient has locations across the world, with three main delivery centers in India Hyderabad, Pune, and Bangalore. We offer the flexibility to work in different delivery sites while working closely with our customers at the same time.

Whatever your particular area of expertise, at Cyient there is opportunity for personal growth. With the breadth of customers, projects, and the sectors that we are active in there are unique and exciting career paths to explore.

We are a fast growing and expanding organization and we want you to join us in our journey in designing the chips of the future!

Apply today!

For more information: https://www.cyient.careers/careers/get-to-know-us

Job Description

Mandatory:

1. Experience in RAL, UVM and SVA(SystemVerilog Assertions)
2. Need to lead a team of 4 people, with client and manage projects.

3. 10yrs of Digital Verification is mandatory

4. Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies

5. Knowledge of Perl/TCL, MAkefile is Must

Good to have:

Experience in Automobile projects preferred.

Experience in Automotive Safety Integrity Level (ASIL) is preferred.
Experience with RTL concepts
Experience with AHB/AXI protocol
Expertise in PCI-e/USB/Ethernet/Switch protocol is an added advantage
You will report to Verification manager
You will Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level
Need to will Develop IP level/SoC level test plans based on the design/architectural specs.
You will work on Coverage Analysis and Coding Run simulations and regressions, debug test failures to identify test case issues and RTL design issues
You will Develop block/full chip level verification environment and its components

Skills & Experience SystemVerilog, SystemVerilog Assertions, Universal Verification Methodology (UVM)

Cyient is an Equal Opportunity Employer.

Cyient recruits, employs, trains, compensates, and promotes regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender, gender identity or expression, veteran status, and other protected status as required by applicable law. We are proud to be a diverse and inclusive company where our people can focus their whole self on solving problems that matter.

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