Technical Manager – Memory Layout 23 views

Job Description : As a leading Engineering and technology solutions company, Cyient’ s Semiconductor business unit is a key contributor to our success. With several blue-chip customers across the world, we are proud to work on cutting edge technolog

Job Description : As a leading Engineering and technology solutions company, Cyient’ s Semiconductor business unit is a key contributor to our success. With several blue-chip customers across the world, we are proud to work on cutting edge technology, shortening development lead times, improving performance, and enabling the technology of tomorrow. Cyient brings more than 20 years of experience in semiconductor and software systems solutions and services. We offer a complete capability across the semiconductor value chain, from design services to custom turnkey ASIC solutions. Our strong technical and domain expertise with a robust partnership ecosystem makes us a trusted global semiconductor partner, giving our engineers the opportunity to work on cutting edge projects, to make a difference and to develop themselves. Why work for Cyient: Our Semiconductor team works on cutting edge technology from AI led chip design to IOT and embedded intelligence. This is your chance to work for an innovative team and build your technical prowess. Our engineers have the opportunity to work across the product lifecycle. Are you looking to expand your skills across the value chain Our project leads recognize talent and growth aspirations, helping you expand your technical skills. Our semiconductor business serves multiple industries such as industrial, medical, and automotive. We are uniquely positioned to bring innovation from each domain for our custom ASIC solutions and semiconductor services. Cyient has locations across the world, with three main delivery centers in India – Hyderabad, Pune, and Bangalore. We offer the flexibility to work in different delivery sites while working closely with our customers at the same time. Whatever your particular area of expertise, at Cyient there is opportunity for personal growth. With the breadth of customers, projects, and the sectors that we are active in there are unique and exciting career paths to explore. We are a fast growing and expanding organization and we want you to join us in our journey in designing the chips of the future! Apply today! For more information: Job Description Memory Layout Engineer General Summary Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. The responsibilities of this role include: Works under close supervision. Responsible for own work. Decision-making is limited. Impact of decisions is readily apparent. Errors made typically only impact timeline (i.e., require additional time to correct)..Requires verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in the subject area..Most tasks require multiple steps which can be performed in various orders some planning and prioritization must occur to complete the tasks effectively mistakes may result in some rework..Some creativity may be required to troubleshoot technical problems or deal with novel circumstances..Deductive problem solving is required to solve moderately complex problems most problems have defined processes of diagnosis/detection some limited data analysis may be required.The responsibilities of this role do not include: .Does not provide supervision to others..Does not have financial accountability..Has no influence over key organizational decisions..Does not have a role in strategic planning.PRINCIPAL DUTIES AND RESPONSIBILITIES: .Reads and interprets straightforward project requirements, specifications, and schematics with limited guidance to understand block-level design needs..Builds block level layouts and floorplans with some direction based on basic understanding of layout techniques, design elements, and electronic principles (e.g., currents, resistance, parasitic)..Applies fundamental understanding of established guidelines, processes, design rule manuals, and checklists to help develop high-quality, accurate designs that meet standards..Tests and validates block level designs against specifications with some guidance using layout and verification tools (e.g., Cadence, LVS, rmap) to identify errors..Gathers information and conducts basic analyses and sign-off to identify where an issue has occurred troubleshoots and debugs technical issues with minimal guidance..Learns new processes and practices to accomplish work and recognizes ways to improve existing ones..Seeks to expand knowledge of industry trends and developments related to mask layout tools and techniques works with team members to apply concepts to one’s work..Adapts to moderate changes and setbacks with some guidance in order to manage pressure and meet deadlines..Executes individual project priorities, deadlines, and deliverables with minimal supervision..Collaborates with engineers and team members to understand needs, share status updates, and escalate issues.1-2 years of experience in Custom layout, Std cell and Memory Layout design.Memory Leafcell layout design from scratch till top level integration.Good knowledge on different types of memory architecture.Good knowledge in optimized layout design for better performance.Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.PHYSICAL REQUIREMENTS:Monitors and utilizes computers and test equipment for more than 6 hours a day.Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely. Minimum Qualifications Education: Bachelors – Computer Science, Bachelors – Electrical Engineering, Bachelors – Electronic Engineering, Bachelors – Mathematics, See the required degree associated with years of work experience Work Experiences: 5+ years experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design) with Associate’s degree in Computer Science, Mathematics, Electrical Engineering or related field.4+ years experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design) with High School Diploma or equivalent. Certifications: Skills: Preferred Qualifications Education: Masters – Electrical Engineering, Masters – Electronic Engineering, Masters – TechnologyWork Experiences:2+ years experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design). ,1+ years experience designing custom layouts in a specific relevant technology (e.g., FINFET, CMOS, GATE ARRAY). Certifications:Skills: Analog Layout, Cadence Virtuoso Layout Suite, Hardware Design, Hardware Simulation, LinuxApplicants: If you need an accommodation, during the application/hiring process Skills & Experience Assembly Code, C Standard Library, Floating Point, Memory, Memory Architecture, Memory Interfaces, Memory Layout, Memory Layout Design, Memory Management Cyient is an Equal Opportunity Employer. Cyient recruits, employs, trains, compensates, and promotes regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender, gender identity or expression, veteran status, and other protected status as required by applicable law. We are proud to be a diverse and inclusive company where our people can focus their whole self on solving problems that matter.

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